Intel Mobile Road Map

From Mac Guides

This is a guide to the Intel mobile road map as it stands in early 2008.

Note to MacRumors Forums Members: Please update this guide as more information becomes available to ensure accuracy!

Contents 1 Basics 2 CPUs (in order of introduction) 2.1 Merom (65nm) 2.2 Penryn (45nm) 2.3 Nehalem (45nm) 2.4 Westmere (32nm) 2.5 Sandy Bridge (22nm) 3 Chipsets (in order of introduction) 3.1 Santa Rosa 3.2 Montevina 3.3 Calpella 3.4 Sandy Bridge

Basics

Platform - Combination of Processor (CPU), Motherboard Chipset, and Network Interface

There are two components to the motherboard, the CPU and the Motherboard Chipset. The CPUs will only work in certain chipsets but there is overlap between them. Also, the chipset is based on the microarchitecture. The current microarchitecture (for the last few years) has been "Core" microarchitecture. Nehalem is the next generation microarchitecture, and Sandy Bridge is the microarchitecture successor to Nehalem.

Note: Nehalem is an exception in the naming scheme in that it refers to both a processor (Clarksfield, Auburnsdale), a chipset (Calpella), and a microarchitecture (Nehalem). Most people refer to it's chipset properties though when mentioning it.

Second Note: To be extremely accurate, the chipsets that are noted are actually called platforms - ie. Santa Rosa platform, Montevina platform, Calpella platform, etc. A platform has three components - the CPU, the motherboard chipset, and the wireless network interface. But for layman's usage of these terms most people use the motherboard chipset name (Cantiga) as the platform name (Montevina), which while not technically correct is the way it is used on these forums so the same thing has been done here. The confusion arises when discussing future platforms (of which there may be one large one - notably Calpella, which is based on Nehalem processors), but which may have multiple motherboard chipsets (currently unknown names of future chipsets but there are likely others coming in the future).

Intel's roadmap alternates between die shrinks and new microarchitectures, one of which happens roughly every year.

CPUs (in order of introduction)

Merom (65nm)

• Fits in Santa Rosa Chipset
• Designed for processing power

Penryn (45nm)

• Fits in Santa Rosa, Montevina, and possibly Calpella Chipsets
• Designed for power efficiency
• Features:

1. Support for SSE4 instruction set (beneficial for media applications that support this (video encoding work, etc))
2. 5-15% performance increase over Merom
3. Lower power consumption = More battery life
4. Higher L2 Cache on certain chips

Nehalem (45nm)

• Due in 2009
• Fits in Calpella Chipset
• Features (rumored):

1. Intel Quick Path Interconnect: Nehalem processors will utilize a new point-to-point processor interconnect called the Intel QuickPath Interconnect. This replaces the outdated FSBs which Intel has been using for many years and directly connect the RAM to the CPU
2. Hyperthreaded, Scalable Processing ability: The Nehalem CPU is apparently able to utilize as few or as many cores as needed for the tasks and programming infrastructure it has to process. This means that if a program is not optimized to use multiple cores (very common) then the cores that are being used could be overclocked and the other cores could be underclocked to remain within the heat specifications of the CPU. This would be the first truly scalable processor.
3. On-Die Cache Controller
4. L1,L2,L3 Cache
5. Possible on board graphics controller
6. Intel considers Nehalem the most dramatic change in microarchitecture since the Pentium Pro in 1996

• The two processors (rumored) to be introduced in Q2 2009 are:

1. Auburnsdale: Dual-Core, 4MB L2 Cache, 35-45W TDP, onboard GPU core
2. Clarksfield: Quad-Core, 8MB L3 Cache, 45-55W TDP, no onboard GPU core

Westmere (32nm)

• Formerly known as Nehalem-C
• Due in 2009
• Possibly fits in Calpella, Sandy Bridge Chipsets, but unknown currently
• Details unknown currently

Sandy Bridge (22nm)

• Currently unnamed, but Sandy Bridge (also the name of the unnamed chipset that will support it) is a common term used to refer to it
• Due in 2010
• Fits in Sandy Bridge Chipset

Chipsets (in order of introduction)

Santa Rosa

• Based on "Core" microarchitecture
• Utilizes Crestline chipset
• 4th Generation Centrino Platform
• Houses Merom and Penryn CPUs

Montevina

• Due in Q2 '08
• Based on "Core" microarchitecure
• Utilizes Cantiga chipset
• 5th Generation Centrino Platform
• Houses Penryn CPUs
• Features:

1. Supports Penryn processors up to 3.06 GHz
2. Lower power requirements
3. 1066MHz FSB (compared to 800MHz for Santa Rosa)
4. DDR3 RAM clocked up to 1066MHz (compared to DDR2 up to 667MHz on Santa Rosa)
5. Support for intel turbo memory (optional on Santa Rosa)
6. Onboard gigabit ethernet
7. WiMax

Calpella

• Due in Q2 '09 (with introduction of new chips)
• This is what most people are referring to when they say they are waiting for Nehalem!
• Utilizes an unnamed chipset
• 6th Generation Centrino Platform
• Houses Nehalem and possibly Westmere CPUs (but newer chipsets may need to be developed to hold Westmere CPUs)
• Features:

1. Calpella is designed for maximization of the raw processing power of Nehalem chips by eliminating the bottleneck of the FSB (front side bus) - early benchmarks have seen 100-200% improvements in speed over today's processor+chipset combinations
2. FSB replaced with "Intel Quick Path Interconnect" which connects CPU and RAM directly
3. Supports DDR3 RAM up to 1600MHz - important because a major bottleneck in current systems is the FSB which connects the RAM and CPU. The Nehalem+Calpella boards seek to eliminate that bottleneck based off of the new design and the RAM speeds will likely be quite noticeable and contribute to increased performance. Currently (early-2008) RAM upgrades and FSB upgrades are only slightly noticeable in the range of 20-30% improvement in speeds.
4. Native support for Blu-Ray (and video encoding/decoding tasks)
5. Native support for SSDs, hybrid drives
6. WiMax
7. Nehalem chips may features 1-8 cores but Calpella supported Nehalem chips will support 2-4 cores as of right now.

Sandy Bridge

• No chipset names are known as of now, this is the name of the underlying CPU microarchitecture, but commonly people use this name to describe the chip as well
• The successor to the Nehalem microarchitecture chipsets
• Sandy Bridge Chipset to support 32nm chips: Due in 2010
• Sandy Bridge Chipset to support 22nm chips: Due in 2011
• No other details known