Core 2 Duo

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Intel's Core Microarchitecture, as featured in Core 2 (codenames Merom, Allendale, Conroe and Woodcrest), introduce a large number of improvements over the previous Core Solo and Core Duo (codenamed Yonah) processor range.

1 Improvements
2 Mobile Processors
- 2.1 Core 2 Duo - "Merom" (64-bit, dual-core)
  - 2.1.1 Future Developments
3 Desktop Processors

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Improvements

Improved decoders: Yonah has three instruction decoders, one capable of decoding complex instructions with up to four micro-ops, the other two capable of decoding simple instructions consisting of a single micro-op. Merom has one complex and three simple instruction decoders. Also, the Merom simple instruction decoders can decode many simple SSE instructions which could only be decoded by the complex decoder on Yonah, vastly increasing the number of instructions that can be decoded in SSE heavy code.

Macrofusion: In some cases, the instruction decoder can merge two instructions into one. That is the case for example for a compare instruction followed by a conditional branch, which can now be decoded as a single instruction.

Larger reorder buffer: The reorder buffer is required for Out-of-Order execution (OoO). It keeps track of instructions that cannot yet be executed because they have to wait for the results of other instructions. As long as the reorder buffer is not filled, instructions that are ready for execution can bypass instructions that were issued earlier, but are not ready for execution yet. The reorder buffer has been increased from 40 to 96 entries.

More reservation stations: Reservation stations are needed for instructions that are ready for execution, but need to wait for an execution unit to become available. Reservation stations are needed when a large number of instructions all use the same execution unit. The number of reservation stations is increased from 24 to 32.

More micro-ops despatched/retired per cycle: Merom can despatch (that is, move from the reorder buffer to the reservation stations) four micro-ops per cycle, and also can retire (that is, store results into registers or send them to memory) four micro-ops per cycle, compared to three micro-ops despatched and retired per cycle on Yonah. In addition, Merom often uses fewer micro-ops for the same instructions than Yonah, especially for SSE instructions.

One additional port: Merom has an additional execution port, which can process either ALU instructions (integer instructions) or SSE instructions. As a result, Merom can execute three arithmetic operations (integer, SSE and floating point) with the restriction that there is at most one floating-point addition and one floating-point multiplication per cycle. Yonah could only execute two arithmetic operations per cycle.

Improved SSE operations: Merom is capable of executing 128 bit SSE instructions; on Yonah, these instructions are automatically split into two 64 bit instructions, needing twice the time.

Increased data paths to and from L1 cache: Merom has a 128 bit connection to L1 cache for load and store operations instead of Yonah's 64 bit path. This means that SSE load and store operation can be performed in one instead of two cycles.

Memory disambiguation: Whenever a processor loads data from memory, it has to wait for preceeding store instructions to finish, unless it knows that the store instruction used a different address. In practice this means that loading data from memory has to stall, even though the load and store address later turn out to be different. Merom solves this problem by "guessing" that there is no conflict between stores and loads, and executing instructions again if the guess was wrong. This is done using a technique similar to branch prediction.

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Mobile Processors

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Core 2 Duo - "Merom" (64-bit, dual-core)

Model	Clock Speed	FSB Speed	L2 Cache	TDP	Socket	Release Date	Release Price (USD)	Current Price (USD)
Core 2 Duo T5200	1.60 GHz	533 MHz	2 MiB	35W	M - 479 pin	?	?	?
Core 2 Duo T5500	1.66 GHz	667 MHz	2 MiB	35W	M - 479 pin	August 28, 2006	$209	$209
Core 2 Duo T5600	1.83 GHz	667 MHz	2 MiB	35W	M - 479 pin	August 28, 2006	$241	$241
Core 2 Duo T7200	2.00 GHz	667 MHz	4 MiB	35W	M - 479 pin	August 28, 2006	$294	$294
Core 2 Duo T7400	2.16 GHz	667 MHz	4 MiB	35W	M - 479 pin	August 28, 2006	$423	$423
Core 2 Duo T7600	2.33 GHz	667 MHz	4 MiB	35W	M - 479 pin	August 28, 2006	$637	$637

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Future Developments

Low voltage variants are set for Q1 2007. In Q2 2007 Intel plans to ship "Santa Rosa". [1] This will be the new incarnation of the Centrino mobile line. It will sport an 800 MHz Front Side Bus, 802.11n, the new Socket P for future mobile chips, and GMA X3000. [2].

Desktop Processors

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Core 2 Duo - "Allendale" (64-bit, dual-core)

Model	Clock Speed	FSB Speed	L2 Cache	TDP	Socket	Release Date	Release Price (USD)	Current Price (USD)
Core 2 Duo E4300	1.80 GHz	800 MHz	2 MiB	65W	LGA775	Q1 2007	TBD

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Notes

Contrary to popular belief, the E6300 and E6400 are not code-named Allendale [3].

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Future Developments

See Millville.

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Core 2 Duo - "Conroe" (64-bit, dual-core)

Model	Clock Speed	FSB Speed	L2 Cache	TDP	Socket	Release Date	Release Price (USD)	Current Price (USD)
Core 2 Duo E6300	1.86 GHz	1066 MHz	2 MiB	65W	LGA775	July 27, 2006	$183	$183
Core 2 Duo E6400	2.13 GHz	1066 MHz	2 MiB	65W	LGA775	July 27, 2006	$224	$224
Core 2 Duo E6600	2.40 GHz	1066 MHz	4 MiB	65W	LGA775	July 27, 2006	$316	$316
Core 2 Duo E6700	2.67 GHz	1066 MHz	4 MiB	65W	LGA775	July 27, 2006	$530	$530